1. Field of the Invention
The present invention relates to a semiconductor member and a semiconductor device employing it, and more particularly to a semiconductor member and a semiconductor device having a hetero-structure.
2. Description of the Prior Art
Prior-art field effect transistors employing heterostructures have basically had energy band structures shown in FIGS. 1 and 2 or these structures in which the positions of two semiconductor layers (11) and (12) are replaced with each other. As the thicknesses of the respective layers, in general, the semiconductor layer (11) of small forbidden band width is set at approximately 0.5-1.0 .mu.m, and the semiconductor layer (12) of great forbidden band width at 0.05-0.1 .mu.m. The device of FIG. 1 and the device of FIG. 2 differ in that, in the former case, carriers are supplied from the semiconductor layer (12) of great forbidden band width doped in the n-type (numeral 14 designates donor atoms), whereas in the latter case, they are supplied from a source electrode. In both the cases, however, the carriers (15) are confined in a triangular potential which appears on the side of a hetero-interface closer to the semiconductor layer (11) of small forbidden band width, and they are caused to travel to the semiconductor layer (11) which is a layer of high purity. Thus, the carriers which are hardly susceptible to scattering attributed to donor impurity ions (16) can be caused to travel, and a high mobility is attained.
On the other hand, as to transistor operations, the device of FIG. 1 essentially operates in the depletion type (hereinbelow, abbreviated to "D-type") being normally-on because the carriers are supplied from the donor impurities so that the source and drain of the device are normally connected electronically. In contrast, the device of FIG. 2 essentially operates as the enhancement type (hereinbelow, abbreviated to "E-type") being normally-off for the reason that, only when a positive voltage is applied to the gate (13) of the device, the carriers are induced in a channel to connect the source and drain of the device, whereas when no voltage is applied to the gate (13), the source and drain are not connected. Accordingly, contrivances have been necessary in case of forming both the E-type and the D-type on an identical substrate for the purpose of integration. (In the ensuing description, GaAlAs will be exemplified as a semiconductor of great forbidden band width, and GaAs as a semiconductor of small forbidden band width. The invention, however, is similarly applicable to other combinations of materials adapted to form heterojunctions, for example, Al.sub.y Ga.sub.1-y As-Al.sub.x Ga.sub.1-x As, GaAs-AlGaAsP, InP-InGaAsP, InP-InGaAs, InAsGnAsSb, and InGaAs-InAlAs.)
More specifically, in the case of the device in FIG. 1, The GaAlAs layer (12) doped in the n-type is rendered thin to realize the E-type. The reason why the E-type is formed is as follows. When the GaAlAs layer (12) is thin, only the carriers within the GaAlAs layer (12) are insufficient for forming a Schottky contact, and also the carriers within the GaAs layer (11) are used. As a result, the carriers (15) are extinguished within the triangular potential, and only when a positive voltage greater than a threshold voltage is applied to the gate of the device, carriers are induced, so that the E-type device is formed. Herein, in a case where the doping concentration of the GaAlAs layer is 2.times.10.sup.18 cm.sup.-3 by way of example, the device becomes the D-type with a thickness of 0.07 .mu.m and the E-type with a thickness of 0.06 .mu.m. Accordingly, a precise etching technique for the GaAlAs layer (12) has been required for separately forming the E-type or the D-type by the use of the device in FIG. 1. This has caused the difficulties that labor is expended and that the etching must be accurately performed in the thickness direction of the layer.
In the case of the device in FIG. 2, the donor impurities are introduced into the non-doped GaAlAs layer (12), and the carriers are induced in the channel directly under the gate, whereby the E-type can be changed to the D-type. Here, the processes of diffusion, ion implantation etc. are used for introducing the impurities to serve as donors into the GaAlAs layer (12). In any case, however, the distribution of the impurities in the thickness direction of the layer assumes a skirt trailing shape, which has incurred the disadvantage that the donor impurities spread, not only within the GaAlAs layer (12), but also into the GaAs layer (11), to lower the mobility of the carriers.
Also with the semiconductor device of the inverse structure in which the positions of the GaAs layer (11) and the GaAlAs layer (12) in FIG. 1 or FIG. 2 are replaced with each other, the separate formation of the E-type or the D-type is equally or more difficult. Originally, once the inverse structure of FIG. 1 has been formed, the GaAlAs layer (12) cannot be thinned.
As thus far described, when it is intended to fabricate an integrated circuit by simply forming the individual semiconductor devices shown in FIG. 1 or FIG. 2 or having the inverse structure and thereafter forming the E-type and the D-type separately, the difficulties have been involved disadvantageously.